1. Field of the Invention
The present invention relates to image display apparatuses, and particularly to a technique for enlarging the operational margin of writing of an image display signal.
2. Description of the Background Art
Flat panel displays are widely used in order to display images with reduced space and reduced power consumption. In flat panel displays, pixels are arranged in a matrix on an image display panel. Each pixel includes a display element such as a liquid-crystal element and a select transistor for transmitting an image display signal (hereinafter referred to as “display signal”) to the display element.
Gate lines (scanning lines) are arranged in correspondence with the rows of pixels, and data lines for transmitting the display signal are arranged in correspondence with the columns of pixels. To each gate line, the gates of the select transistors of the pixels of the corresponding row are connected. To each data line, one current electrodes of the select transistors of the pixels of the corresponding column are connected.
The select period of a gate line is determined by the horizontal scanning period of the display signal. For example, in the NTSC system in which the number of horizontal scanning lines is 525, one horizontal scanning period is 64 μS. As this period is so short, the active matrix system is usually utilized in which one gate line at a time is brought into a selected state (active state) according to the horizontal scanning period, and all select transistors of that line are made conductive and the display signal is written into the pixels. In this system, the gate lines are kept in a non-selected state (inactive state) during the vertical scanning periods other than their own selected periods, and the corresponding select transistors are kept in a non-conducting state in those periods. Accordingly, the pixels maintain the display signal and drive the display elements for one field period and display the corresponding display signal.
For such image display apparatuses, various schemes are devised to enable stable and correct display of images (for example, Japanese Patent Application Laid-Open Nos. 2005-3714, 2008-176269, and 11-265172 (1999), which are hereinafter referred to as Patent Documents 1 to 3, respectively).
In the display apparatus of Patent Document 1, a gate line inactivation detecting circuit (2) is provided at the ends of the gate lines on the side opposite to the connection with the gate line driving circuit (FIG. 19), and a latch instruction signal (LAT) provided as its output is used to operate a second latch circuit (114) for defining the timing of transmission of the display signal to a multiplexer (116). This prevents the overwriting of the previous pixel line with the next pixel line display signal. However, by this method, display errors may occur when the delay time of the gate line driving signal is large.
In the display apparatus of Patent Document 2, a gate clock generating portion (400) for generating clock signals for driving the gate line driving circuit detects the delay time of a gate line driving signal (Von), and narrows the pulse widths of clock signals (CKV, CKVB) according to the delay time (FIG. 2). Then, the pulse width of the gate line driving signal is made approximately equal to one horizontal scanning period (1H), and this prevents the overwriting of the pixels with the next pixel line display signal. However, when the pulse widths of the clock signals are narrowed, their driving abilities are lowered, and the operational margin of the gate line driving circuit is lowered.
In the display apparatus of Patent Document 3, the delay time of the gate line driving signal is detected, and according to the delay time, a timing adjusting circuit (31) delays a control signal (LTHXU) for a latch circuit (13) that defines the timing of sending the display signal to a D/A converter (FIG. 9). This prevents the overwriting of pixels with the next pixel line display signal, but, like Patent Document 1, display errors may occur when the delay time of the gate line driving signal is large. Also, the costs of the display apparatus are increased because the circuit that detects the delay time of the gate line driving signal is provided outside of the display apparatus.
In this way, for conventional display apparatuses, it was difficult to prevent display errors while ensuring operational margin when the delay time of the gate line driving signal is large.